AT87251G2D-3CSUM【PDF 11/77 页】IC 8051 MCU 32K OTP 24MHZ 40DIP

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AT/TSC8x251G2D

4135F–8051–11/06

Table 12.

Configuration Byte 1

UCONFIG1

Notes: 1. The CSIZE is only available on EPROM/OTPROM products.

2. Two or four bytes are transparently popped according to INTR when using the RETI

instruction. INTR must be set if interrupts are used with code executing outside

region FF:.

3. Use only for Step A compatibility; set this bit when WSB1:0# are used.

7654

3210

CSIZE

INTR

WSB

WSB1#

WSB0#

EMAP#

Bit

Number

Bit Mnemonic

Description

CSIZE

TSC87251G2D

On-Chip Code Memory Size bit(1)

Clear to select 16 KB of on-chip code memory (TSC87251G1D

product).

Set to select 32 KB of on-chip code memory (TSC87251G2D product).

TSC80251G2D

TSC83251G2D

Reserved

Set this bit when writing to UCONFIG1.

Reserved

Set this bit when writing to UCONFIG1.

Reserved

Set this bit when writing to UCONFIG1.

4INTR

Interrupt Mode bit(2)

Clear so that the interrupts push two bytes onto the stack (the two lower

bytes of the PC register).

Set so that the interrupts push four bytes onto the stack (the three bytes

of the PC register and the PSW1 register).

3WSB

Wait State B bit

(3)

Clear to generate one wait state for memory region 01:.

Set for no wait states for memory region 01:.

2WSB1#

Wait State B bits

Select the number of wait states for RD#, WR# and PSEN# signals for

external memory accesses (only region 01:).

WSB1#

WSB0#

Number of Wait States

1WSB0#

0EMAP#

On-Chip Code Memory Map bit

Clear to map the upper 16 KB of on-chip code memory (at FF:4000h-

FF:7FFFh) to the data space (at 00:C000h-00:FFFFh).

Set not to map the upper 16 KB of on-chip code memory (at FF:4000h-

FF:7FFFh) to the data space.

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